The emergence of mobile consumer electronics, such as cellular telephones, notebook computers, personal digital assistants (PDAs), and MP3 players to name but a few, has increased the demand for compact, high performance memory devices. In many ways, the modern development of semiconductor memory devices may be viewed as a process of providing the greatest number of data bits at defined operating speeds using the smallest possible device. In this context, the term “smallest” generally denotes a minimum area occupied by the memory device in a “lateral” X/Y plane, such as a plane defined by the primary surfaces of a printed circuit board or module board. Not surprisingly, restrictions of the tolerable lateral area occupied by a memory device have motivated memory device designers to vertically integrate the data storage capacity of their devices. Thus, for many years now, multiple memory devices that might have been laid out adjacent to one another in a lateral plane have instead been vertically stacked one on top of the other in a vertical Z plane relative to the lateral X/Y plane.
Recent developments in the fabrication of so-called “Through Silicon Vias (TSVs)” have facilitated the trend towards vertically stacked semiconductor memory devices. TSVs are interchip connection elements that pass substantially, if not completely, through a substrate, and are fully contained within the periphery of the stacked substrates. TSVs are distinct from and have largely replaced vertical connection elements running up the outer edges of stacked memory devices. Such external wiring (i.e., wiring disposed on the periphery) was conventionally required to operatively connect the stacked devices. But this wiring increases the overall lateral area occupied by the stacked device, and typically requires interposing layers between adjacent substrates in the stack. Because TSVs pass vertically upward through a substrate, no additional lateral area is required beyond that defined by the periphery of the largest substrate in the stack. Further, TSVs tend to shorten the overall length of certain critical signal paths through the stack of devices, thereby facilitating faster operating speeds.
Stacked semiconductor memory devices are one type of three dimensional (3D) integrated circuits. That is, from the standpoint of other system components such as a memory controller, a 3D memory apparatus functions as an integral memory device. Data write and data read operations are processed by the 3D memory device in order to store write data or retrieve read data in ways generally applicable to non-stacked (i.e., single substrate) memory devices. Yet, the 3D memory apparatus is able to store and provide a great deal more data per unit lateral surface area, as compared to a non-stacked memory device.
Thus, through the use of TSVs or similar stack fabrication processes, memory (and other) apparatuses implemented with a plurality of vertically stacked substrates or chips are able to store and provide a large amount of data using a single integrated circuit having a relatively small lateral surface area footprint. However, surface area efficient storage and retrieval of data from a 3D memory apparatus poses a number of related challenges to the memory apparatus and system designer.
Consider for the moment the conventional single layer Dynamic Random Access Memory (DRAM) 10 shown in FIG. 1. A DRAM memory cell array 12 comprises a great number of individual memory cells arranged in relation to a matrix of row and column signal lines. Each memory cell is able to store write data in response to a write command and provide read data in response to a read command received from an external device (not shown), such as a memory controller or processor. Read/write commands result in the generation of certain control signals (e.g., a row address, a column address, enable signals, etc.), which, along with certain control voltages, are applied to memory cell array 12 through related peripheral devices, such as row decoder 11 and column decoder 13.
During a write operation, write data (i.e., data intended to be stored in memory cell array 12) passes from the external circuit (e.g., an external memory, an external input device, a processor, a memory controller, a memory switch, etc) to data registers 15-4 of the peripheral blocks 15. Once stored in data registers 15-4, the write data may be written to memory cell array 12 through conventional structures and techniques, which may include, for example, sense amplifier and write driver circuitry 14.
During a read operation, applied control voltages, as well as the control signal outputs of row decoder 11 and column decoder 13 generally cooperate to identify and select one or more memory cell(s) in memory cell array 12 and facilitate the provision of signals indicating the value of data stored in the memory cell(s). The resulting “read data” typically passes through read sense amplifier 14 to be stored in data registers 15-4. Read data stored in data registers 15-4 may be subsequently provided to the external circuit under the control of read control circuit 15-1.
Looking now collectively at FIGS. 2a and 2b, an exemplary TSV-based 3D stacked memory chip 20 is illustrated, and which typically consists of multiple slave chips 21 and a master chip 22, as well as an underlying substrate 23. Also illustrated are the TSVs 24 passing through the various chips, and interconnected using TSV bonding pads 25. This exemplary embodiment of a 3D TSV memory 20 requires different chip designs for the slave 21 and master 22 chips. Specifically, the master chip 22 does not need any specific logic block to test memory cell arrays; however, the slave chips 21 need additional logic blocks 26 to test and sort memory cell pass and fail. Also, the master chip 22 has an I/O interface 27 that is connected externally through package balls or pins, and also includes all DRAM operation relevant logic blocks 28, such as write/read control logic, refresh control, and internal power supplies (e.g., VBB, VPP, VBLP, VPLT, VDL, etc.).
These internal power supplies need to be regulated to get proper voltage levels no matter what the process voltage temperature (PVT) conditions, or any other conditions affecting performance, may be. Accordingly, what is needed in the art are techniques and related structures for effectively regulating power among slave chips in a 3D stacked multichip package that do not suffer from the deficiencies found in conventional approaches. The disclosed principles provide such solutions, as discussed in detail below.